1. Field of the Invention
The present invention relates to a phase-difference detector used for a PLL (phase-locked loop), which can be applied to optical communication or the like.
This application is based on Patent Application No. Hei 10-160045 filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In a serial communication system such as an optical communication system, it is necessary to extract a clock component (or signal) from a serial data sequence at the receiving side, so as to receive data based on the extracted clock signal. The circuit for extracting a clock signal from a serial data sequence is called a clock-recovery circuit, which is a very important element for realizing an LSI used for the serial communication. This clock-recovery circuit is a kind of PLL, and can be generally realized using the structure shown in FIG. 6.
In FIG. 6, reference symbol PD indicates a phase-difference detector, which detects a phase difference between a clock signal output from the VCO (voltage-controlled oscillator) and an input data-signal sequence, and determines whether the current phase is advanced or delayed and outputs the determined results as phase-difference signals. The phase-difference signals, a set of pulse signals whose pulse widths are proportional to each phase difference, are output from the xe2x80x9cdownxe2x80x9d terminal and the xe2x80x9cupxe2x80x9d terminal at the output side. In this clock-recovery circuit, these xe2x80x9cdownxe2x80x9d and xe2x80x9cupxe2x80x9d signals are fed back (as an input signal) via a charge-pump circuit and a low-pass filter into the VCO, so that the phase of the extracted clock signal corresponds to that of the data input signal.
An example circuit of the conventional phase-difference detector is shown in FIG. 7. This circuit is disclosed by C. R. Hogge in xe2x80x9cA Self Correcting Clock Recovery Circuitxe2x80x9d, IEEE Transactions on Electron Devices, Vol. ED-32, No. 12, pp. 2704-2706, December, 1985.
FIG. 8 is a timing chart showing the operations of the circuit of FIG. 7. This circuit comprises a flip-flop circuit FF1 into which a signal is input at (timing corresponding to) a rising edge of the clock signal, another flip-flop circuit FF2 which operates at (timing corresponding to) a decaying (or falling) edge of the clock signal, and two exclusive OR circuits XOR1 and XOR2.
The exclusive OR between the data input signal xe2x80x9cdinxe2x80x9d and the output of FF1 is calculated so as to detect a phase difference between the clock signal and the data input signal, and a pulse signal whose pulse width corresponds to the detected phase difference is output from the xe2x80x9cupxe2x80x9d terminal. On the other hand, when a pulse signal is output from the xe2x80x9cupxe2x80x9d terminal, a pulse signal whose pulse width corresponds to half of the clock period is output from the xe2x80x9cdownxe2x80x9d terminal.
As shown in the section from 3.0 ns to 4.0 ns in the horizontal axis in FIG. 8, when the difference between the rise timing of the clock signal and the transition timing of the data input signal becomes half of the clock period, the pulse width of the signal from the xe2x80x9cupxe2x80x9d terminal is half of the clock period. Therefore, the circuit as shown in FIG. 7 can detect the phase difference, and can be applied to the PD in FIG. 6, thereby realizing a clock-recovery circuit.
The circuit in FIG. 7 also has a data-recovery function for receiving and outputting data based on the extracted clock signal. That is, both (i) detection of the phase difference between the input data sequence and the extracted clock signal and (ii) data-receiving operation can be executed using the circuit of FIG. 7; thus, the structure of the LSI used for a communication system can be simplified.
However, in the phase-difference detector as shown in FIG. 7, a clock signal whose frequency can agree with the frequency of the data input signal (i.e., the data rate) is necessary. That is, as shown in the timing chart of FIG. 8, if the transition (between the high level and the low level) of the data input signal appears with a minimum period of 0.25 ns (see the section between 3 ns to 4 ns in FIG. 8), then the period of the clock signal must also be 0.25 ns. Here, each xe2x80x9ctransitionxe2x80x9d of the data input signal corresponds to a period from a rise to a decay (or fall) of the data input signal, or to a period from a decay to a rise of it.
Here, the period of the high level or the low level of the clock signal is 0.125 ns, that is, half of the clock period. Therefore, the clock signal must maintain a frequency two times as high as the data rate.
This requirement causes a serious problem, in particular, in a circuit design aimed at high-speed operations using the maximum efficiency of each device to be used. The possible frequency of the clock signal to be generated and divided is basically determined depending on the efficiency or performance of the device; thus, in the conventional circuit such as the above, the possible data rate is half or less of the device efficiency.
In order to solve the above problem, a circuit for receiving data using both the rising edge and the decaying edge of the clock signal is used for receiving a high-speed data input signal. A sample circuit is shown in FIG. 9. The data input signal input from the terminal xe2x80x9cdinxe2x80x9d is distributed into two lines. The data signal received at the decay timing of the clock signal is output from terminal xe2x80x9cdout0xe2x80x9d, while the data signal received at the rise timing of the clock signal is output from terminal xe2x80x9cdout1xe2x80x9d. In this circuit, a clock signal whose frequency is half that of the data rate of the data input signal can be used. For example, a data input signal of 4 Gbps can be received using a clock signal of 2 GHz. That is, by using a device having the same performance as that used in the circuit of FIG. 7, high-speed operations at a frequency twice as high as that of the circuit of FIG. 7 can be expected. In addition, a plurality of the circuits as shown in FIG. 9 can be connected in a xe2x80x9ctreexe2x80x9d form and the frequency of the clock signal of each circuit can be half of the frequency of the clock signal of the previous circuit, thereby constructing a multi-bit output demultiplexer having a simple structure.
However, in the circuit as shown in FIG. 9, two distributed output signals are obtained with respect to a data input signal. In this case, accurate phase-difference information cannot be obtained only by simply calculating the exclusive OR between the data input signal and the output signal from the flip-flop circuit as calculated in the circuit of FIG. 7. The reason for this is as follows. In the circuit of FIG. 7, the data signal is always obtained from the output of flip-flop FF1; however, the circuit of FIG. 9 has different operations. For example, a data input signal which existed at each even-numbered position in the original serial data-signal sequence is output from FF1, while a data input signal which existed at each odd-numbered position in the original serial signal sequence is output from FF3. Therefore, even if the output of the xe2x80x9cdinxe2x80x9d terminal thorough which all data passes and the output of FF1 which includes only half of the information of the data are simply compared, phase-difference information as obtained by the circuit of FIG. 7. cannot be generated in this case.
Accordingly, if the binary-tree type high-speed and simple structure as shown in FIGS. 9 and 10 is applied to the demultiplexer which needs the highest operational frequency so as to operate it at the highest speed, then a separate phase-difference detector is also necessary.
In order to realize a high-speed serial communication circuit, an objective of the present invention is to provide a phase-difference detector which can use a clock signal whose frequency is half of the data rate, receive data at both rise timing and decay timing of the clock signal, and output phase-difference information between the data input signal and the clock signal.
Therefore, the present invention provides a phase-difference detector comprising:
a data input terminal for inputting a data input signal;
a first register circuit for receiving the data input signal from the data input terminal in synchronism with the decay timing of a base clock signal;
a second register circuit for receiving the data input signal from the data input terminal in synchronism with the rise timing of the base clock signal;
a first exclusive OR circuit, two input terminals of which are connected with an input terminal and an output terminal of the first register circuit;
a second exclusive OR circuit, two input terminals of which are connected with the output terminal of the first register circuit and an output terminal of the second register circuit;
a first AND circuit, the inverted signal of an output of the first exclusive OR circuit and the inverted signal of the base clock signal being input into two input terminals of said first AND circuit;
a second AND circuit, the inverted signal of an output of the second exclusive OR circuit and the base clock signal being input into two input terminals of said second AND circuit;
a third AND circuit, the output of the first exclusive OR circuit and the inverted signal of the base clock signal being input into two input terminals of said third AND circuit; an OR circuit, outputs of the second and third AND circuits being input into two input terminals of said OR circuit;
a first output terminal for outputting an output of the first AND circuit; and
a second output terminal for outputting an output of the OR circuit.
The phase-difference detector may further comprise a third register circuit for receiving a signal in synchronism with the rise timing of the base clock signal, an input terminal of which is connected with the output terminal of the first register circuit, wherein two distributed data signals are output from output terminals of both the second and third register circuits, thereby realizing a demultiplexing function.
The present invention also provides a clock-recovery circuit using a phase-difference detector as explained above, comprising:
the phase-difference detector for comparing an output of a voltage-controlled oscillator and the data input signal; and
a charge-pump circuit, two output signals of the phase-difference detector, down and up signals, being input into two input terminals of said charge-pump circuit;
a low-pass filter, an output of the charge-pump circuit being input into an input terminal of said low-pass filter; and
the voltage-controlled oscillator, an output of the low-pass filter being input into an input terminal of said voltage-controlled oscillator, for outputting the base clock signal.
That is, using the phase-difference detector according to the present invention in a clock-recovery circuit enables use of a clock signal whose frequency is half of the data rate so that the frequency of the clock signal can be matched with the transition frequency of the data input signal. Therefore, by using a device having the same performance as that of a device used in a conventional circuit, high-speed operations at a frequency twice as high as that of the conventional circuit can be realized.
Furthermore, two distributed data signals can be simultaneously obtained by using both rising and decaying edges of the base clock signal. Accordingly, a high-speed tree-type demultiplexer can be realized, thereby realizing a higher LSI used for serial communication.